I. Field of the Disclosure
The technology of the disclosure relates generally to static random access memory (SRAM) bit cells, and particularly to the physical design of SRAM bit cells.
II. Background
Processor-based computer systems include memory for data storage. Different types of memory exist, each possessing certain unique features. For example, static random access memory (SRAM) is a type of memory that can be employed in processor-based computer systems. SRAM can store data without the need to periodically refresh the memory, unlike dynamic random access memory (DRAM) for example. An SRAM contains a plurality of SRAM bit cells (also referred to as “bit cells”) organized in rows and columns in an SRAM data array. For any given row in an SRAM data array, each column of the SRAM data array includes an SRAM bit cell in which a single data value or bit is stored. Access to a desired SRAM bit cell row is controlled by wordlines corresponding to read and write operations. Read wordlines provide access for reading a bit stored in an SRAM bit cell via corresponding read ports. Further, write wordlines provide access for writing a bit to an SRAM bit cell via corresponding write ports.
In this regard, an SRAM bit cell may be designed with multiple ports for reading and writing a bit associated with the SRAM bit cell. As a non-limiting example, FIG. 1 illustrates a circuit diagram of a commonly used three-port SRAM bit cell 100 that includes a first read wordline 102, a second read wordline 104, and a write wordline 106. In this manner, the three-port SRAM bit cell 100 is configured to be read via a first read port 108 and a second read port 110, and written to via a write port 112. Further, the three-port SRAM bit cell 100 is configured to store a single bit within two (2) inverters 114, 116, wherein the inverters 114, 116 are cross-coupled to retain an electrical charge representing the data value of the bit.
With continuing reference to FIG. 1, to read the three-port SRAM bit cell 100 via the first read port 108, a first read bitline 118 is pre-charged to a logical ‘1’ value, and the first read wordline 102 is configured to activate a first read access transistor 120. In this manner, if the stored bit has a logical ‘1’ value, the inverters 114, 116 are configured to provide a logical ‘0’ value to a first read access transistor 122. The logical ‘0’ value does not activate the first read access transistor 122, thus preserving the logical ‘1’ value on the first read bitline 118. Conversely, if the stored bit has a logical ‘0’ value, the inverters 114, 116 are configured to provide a logical ‘1’ value to the first read access transistor 122. The logical ‘1’ value activates the first read access transistor 122, thus providing a logical ‘0’ value to the first read bitline 118 via a ground voltage source 124. The second read wordline 104, a second read bitline 126, second read access transistors 128, 130, and the ground voltage source 124 are configured in a similar manner to perform reads via the second read port 110.
With continuing reference to FIG. 1, to write a bit to the three-port SRAM bit cell 100 via the write port 112, the write wordline 106 is configured to activate two (2) write access transistors 132, 134. A value to be written to the three-port SRAM bit cell 100 is provided by a write bitline 136, while a complementary value is provided by a complementary write bitline 138. Thus, to write a logical ‘1’ value, the write wordline 106 activates the write access transistors 132, 134, and the write bitline 136 provides a logical ‘1’ value while the complementary write bitline 138 provides a logical ‘0’ value. Such a configuration of logical values causes the inverters 114, 116 to store a logical ‘1’ value. Conversely, to write a logical ‘0’ value, the write wordline 106 activates the write access transistors 132, 134, and the write bitline 136 and the complementary write bitline 138 provide a logical ‘0’ value and a logical ‘1’ value, respectively. In this manner, the three-port SRAM bit cell 100 may be accessed for independent read operations using the first read wordline 102 and the second read wordline 104, and accessed for a write operation using the write wordline 106.
While the circuit design of the three-port SRAM bit cell 100 in FIG. 1 provides the functionality described above, the physical design may be a source of performance limitations. Notably, as the gate length of the first read access transistors 120, 122, the second read access transistors 128, 130, the write access transistors 132, 134, and transistors associated with the inverters 114, 116 continues to decrease to fourteen (14) nanometers (nm) and below, design rules associated with certain fabrication techniques, such as self-aligned-double-patterning (SADP), require that particular metal levels have a unidirectional orientation. However, designing the three-port SRAM bit cell 100 to conform to such design rules may increase the complexity of the corresponding physical design. An increase in the complexity of the physical design commonly results in reducing the width of the first and second read wordlines 102, 104 and the width of the write wordline 106. As the width of the first and second read wordlines 102, 104 and the write wordline 106 decreases, the resistance of each wordline 102, 104, 106 increases. An increase in the resistance of the first and second read wordlines 102, 104 and the write wordline 106 increases the access time of each wordline 102, 104, 106, thus reducing the performance of the three-port SRAM bit cell 100. Therefore, it would be advantageous to design a three-port SRAM bit cell with a physical design that conforms to design rules while having wordlines with decreased resistance, thus increasing the performance of the three-port SRAM bit cell.